International journal of VLSI design & Communication Systems
( VLSICS )

A New Full Adder Cell for Molecular Electronics  [Pdf]
Mehdi Ghasemi, Mohammad Hossein Moaiyeri and Keivan Navi, Shahid Beheshti University G.C., Iran

A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates  [Pdf]
Md. Sazzad Hossain¹, Md. Rashedul Hasan Rakib¹, Md. Motiur Rahman¹,A. S. M. Delowar Hossain¹ and Md. Minul Hasan², ¹Mawlana Bhashani Science & Technology University, Bangladesh and ²Amader Ltd, Bangladesh

FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS - II Based SOC  [Pdf]
Bolla Leela Naresh, N.V.Narayana Rao and Addanki Purna Ramesh, Sri Vasavi Engg College, India

Design of Reversible Sequential Circuit Using Reversible Logic Synthesis  [Pdf]
Md. Belayet Ali, Md. Mosharof Hossin and Md. Eneyat Ullah, Mawlana Bhashani Science and Technology University, Bangladesh

Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate  [Pdf]
Manoj Kumar¹, Sandeep K. Arya¹ and Sujata Pandey²,¹Guru Jambheshwar University of Science & Technology, India and ²Amity University, India

Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level  [Pdf]
M.S.Suma¹ and K.S.Gurumurthy², ¹R.V.College of Engineering, India and ²U.V.College of Engineering, India

A Novel Approach to Minimize Spare Cell Leakage Power Consumption During Physical Design Implementation  [Pdf]
Vasantha Kumar B.V.P¹ , N. S. Murthy Sharma² , K. Lal Kishore³ and Jibanjeet Mishra¹, ¹ Synopsys (India) Pvt. Ltd, India, ² SV Institute of Engineering and Technology, India and ³ JNT University, India

VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology  [Pdf]
Rita M. Shende and Pritesh R. Gumble, Sipna's College of Engineering & Technology, India

An Efficient FPGA Implemenation of MRI Image Filtering and Tumour Characterization Using XILINX System Generator  [Pdf]
S. Allin Christe, M.Vignesh and A.Kandaswamy, PSG College of Technology, India

Design and ASIC Implemenatation of DUC/DDC for Communication Systems  [Pdf]
Naagesh S. Bhat, Green Mil International Ltd., India

Low Power Low Voltage Bulk Driven Balanced OTA  [Pdf]
Neha Gupta, Sapna Singh, Meenakshi Suthar and Priyanka Soni, Mody Institute of Technology and Science, India

Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell  [Pdf]
Viplav A. Soliv and Ajay A. Gurjar, Sipna's college of Engineering & Technology, India

A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs  [Pdf]
Ramya Menon C. and Vinod Pangracious, Rajagiri School of Engineering & Technology, India

Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Technology  [Pdf]
Rajendra Prasad S¹, B K Madhavi² and K Lal Kishore³, ¹ACE Engineering College, India, ²GCET, India and ³JNT University, India

Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Utilization  [Pdf]
Bhavana Pote¹,V. N. Nitnaware¹,and S. S. Limaye², ¹Ramdeobaba Kamla Nehru College of Engg, India and ²Jhulelal Institute of Technology, India

A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits  [Pdf]
Mouna Karmani¹, Chiraz Khedhiri¹, Belgacem Hamdi¹ and Brahim Bensalem²,¹Electronics and Microelectronics Laboratory,Tunisia and ²Intel Corporation, USA

Test Generation for Analog and Mixed-Signal Circuits Using Hybrid System Models  [Pdf]
Tarik NAHHAL¹ and Thao Dang²,¹Hassan II University, Morocco and ²VERIMAG, France

A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic  [Pdf]
P.Prasad Rao and K.Lal Kishore, JNTU-Hyderabad, India

FPGA Implementation of Soft Output Viterbi Algorithm Using Memoryless Hybrid Register Exchange Method  [Pdf]
R .D. Kadam and S. L. Haridas, RTM Nagpur University, India

Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power Applications  [Pdf]
Subhra Dhar¹, Manisha Pattanaik¹, P. Rajaram²,¹ABV-Indian Institute of Information Technology and Management, India and ²Jiwaji University, India

Power Comparison of CMOS and Adiabatic Full Adder Circuits  [Pdf]
Y. Sunil Gavaskar Reddy and V.V.G.S.Rajendra Prasad, JNTUniversity, India

Sub Ten Micron Channel Devices Achieved by Vertical Organic Thin Film Transistor  [Pdf]
Abdul Rauf Khan¹, S.S.K. Iyer²,¹Graphic Era University,India and ²IIT-Kanpur, India

Pipelined Architecture of 2D-DCT, Quantization and ZigZag Process for JPEG Image Compression Using VHDL   [Pdf]
T.Pradeepthi and Addanki Purna Ramesh, Sri Vasavi Engg College, India

Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip   [Pdf]
Rehan Maroofi¹,V. N. Nitnaware¹ and S. S. Limaye²,¹Ramdeobaba Kamla Nehru College of Engg, India and ²Jhulelal Institute of Technology, India

Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA   [Pdf]
Veena M.B and M.N.Shanmukha Swamy, SJCE, India

Design and Implementation of FPGA Based Signal Processing Card   [Pdf]
Priya Gupta¹ and Deepak Gupta²,¹Banasthali University, India and ²Alpine System, India

Design of a CMOS Bandgap Reference with Low Temperature Coefficient and High Power Supply Rejection Performance   [Pdf]
Abhisek Dey and Tarun Kanti Bhattacharyya, Indian Institute of Technology-Kharagpur, India

Area Optimized FPGA Implementation for Generation of Radar Pulse Compression Sequences   [Pdf]
P. Tirumala rao¹, P. Siva kumar¹, Y.V. Apparao², Y. Madhu babu²,¹Vignan institute of information technology, India and ²GITAM University, India

Special Issue on "VLSI - 2011"

Software and Hardware Design Challenges in Automotive Embedded System   [Pdf]
Rajeshwari Hegde¹, Geetishree Mishra¹, K S Gurumurthy²,¹BMS College of Engineering, India and ²UVCE, India

Power Aware Physical Model for 3D ICs   [Pdf]
Yasmeen Hasan, Integral University, India

Linearity and Analog Performance Analysis of Double Gate Tunnel FET: Effect of Temperature and Gate Stack   [Pdf]
Rakhi Narang¹, Manoj Saxena¹, R.S.Gupta²and Mridula Gupta¹,¹University of Delhi, India and ²Maharaja Agrasen Institute of Technology, India

Brauns Multiplier Implementation using FPGA with Bypassing Techniques   [Pdf]
Anitha R and Bagyaveereswaran V, VIT University, India

Modelling and Simulation of 128-Bit Crossbar Switch for Network On Chip   [Pdf]
Mohammad Ayoub Khan¹ and Abdul Quaiyum Ansari², ¹Ministry of Communications and Information Techology, India and ²Jamia Millia Islamia, India

Impact of Interface Fixed Charges on the Performance of the Channel Material Engineered Cylindrical Nanowire MOSFET   [Pdf]
Rajni Gautam¹, Manoj Saxena¹, R.S.Gupta²and Mridula Gupta¹, ¹University of Delhi, India and 2Maharaja Agrasen Institute of Technology, India

Reducing power in using different technologies using FSM architecture   [Pdf]
Himani Mitta, Dinesh Chandra and Sampath Kumar, J.S.S.Academy of Technical Education, India

A BIST Generator CAD Tool for Numeric Integrated Circuits  [Pdf]
Chiraz Khedhiri¹, Mouna Karmani¹ and Belgacem Hamdi^1,2, ¹Electronic & Microelectronics^'LAB, Tunisia and ²ISSAT, Tunisia

A Novel Approach for Lower Power Design in Turbo Coding System  [Pdf]
Dayadi.Lakshmaiah¹, M.V.Subramanyam² and K.Sathaya Prasad³, ¹Sree Dattha Engineering and Science, India, ²Santhi Ram Engineering College, India and ³JNTU, India

Design and test challenges in Nano-scale analog and mixed CMOS technology  [Pdf]
Mouna Karmani, Chiraz Khedhiri and Belgacem Hamdi, Electronics & Microelectronics Laboratory, Tunisia

Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-m technology scale  [Pdf]
M.Sumathi¹ and S.Malarvizhi², ¹Sathyabama University, India and ²SRM University, India

Design of optimized Interval Arithmetic Multiplier  [Pdf]
Rajashekar B.Shettar and R.M.Banakar, BVB College of Engg and Technology, India

Performance of Different CMOS Logic Styles for Low Power and High Speed  [Pdf]
Sreenivasa Rao.Ijjada, Ayyanna.G, G.Sekhar Reddy and V.Malleswara Rao, GITAM University, India

New Design Methodologies for High-Speed Mixed-Mode CMOS Full Adder Circuits  [Pdf]
Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, M.N.N.I.T, India

A New Approach to Design Low Power CMOS Flash A/D Converter  [Pdf]
Sudakar S. Chauhan¹, S. Manabala², S.C. Bose² and R. Chandel³, ¹Graphic Era University, India, ²CEERI, India, ³National Institute of Technology - Hamirpur, India

A Bus Encoding to Reduce Crosstalk Noise Effect in System on Chip  [Pdf]
J.Venkateswara Rao¹ and A.V.N.Tilak², ¹Vignan Institute of Technology & Science, India and ²Gudlavalleru Engineering College, India

High Speed Multiple Valued Logic Full Adder Using Carbon Nano Field Effect Transistor  [Pdf]
Ashkan Khatir, Shaghayegh Abdolahzadegan and Iman Mahmoudi, Islamic Azad University, Iran

Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function  [Pdf]
Deepesh Ranka, Ashwani K. Rana, Rakesh Kumar Yadav, Kamalesh Yadav and Devendra Giri, National Institute of Technology - Hamirpur, India

Physical Scaling Limits of FinFET Structure: A Simulation Study  [Pdf]
Gaurav Saini and Ashwani K Rana, National Institute of Technology - Hamirpur, India

Design and Implementation of Area and Power Optimised Novel Scanflop  [Pdf]
R.Jayagowri¹ and K.S.Gurumurthy², ¹Jawaharlal Nehru Technological University, India and ²Visveswaraya College of Engineering, India

Optimization Techniques for Source Follower Based Track-and-Hold Circuit for High Speed Wireless Communication  [Pdf]
Manoj Kumar¹ and Gagnesh Kumar², ¹Vidya College of Engineering, India and ²NIT - Hamirpur, India

Impact of Strain and Channel Thickness on Performance of Biaxial Strained Silicon MOSFETs  [Pdf]
Neha Sharan and Ashwani K.Rana, National Institute of Technology - Hamirpur, India

Design of a high frequency low voltage CMOS operational amplifier  [Pdf]
Priyanka Kakoty, Tezpur University, India

Design Approach for Fault Tolerance in FPGA Architecture  [Pdf]
Shweta S. Meshram¹ and Ujwala A. Belorkar², ¹Government College of Engineering & Technology, Amravati, India and ²Hanuman Vyayam Prasarak Mandal's College of Engineering & Technology, India

Design and Analysis of Second and Third Order PLL at 450MHz  [Pdf]
B. K. Mishra, Sandhya Save and Swapna Patil, Mumbai University, India

Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology  [Pdf]
Ms. Ujwala A. Belorkar¹ and S.A.Ladhake², ¹Hanuman Vyayam Prasarak Mandal's College of Engineering & Technology, India and ²Sipana's College of Engineering & Technology, India