Design and Analysis of A 32-bit Pipelined MIPS Risc ProcessorFull Text
P. Indira¹, M. Kamaraju² and Ved Vyas Dwivedi¹, ¹CU Shah University, India and ²JNT University, India

Design And Implementation of Combined Pipelining and Parallel Processing Architecture for FIR and IIR Filters Using VHDLFull Text
Jacinta Potsangbam and Manoj Kumar, National Institute of Technology, India

Duty Cycle Corrector Using Pulse Width ModulationFull Text
Meghana Patil¹, Kiran Bailey¹ and Rajanikanth Anuvanahally², ¹BMSCE, India and ²Senior Member IEEE, India

FPQA Implementation of Huang Hilbert Transform for Classification of Epileptic Seizures Using Artificial Neural NetworkFull Text
G.Deepika¹ and K.S.Rao², ¹RRS college of Engineering, India and ²Anurag group of Institutions, India

Efficient Absolute Difference Circuit for SAD Computation On FPGAFull Text
Jaya Koshta, Kavita Khare and M.K Gupta, Maulana Azad National Institute of Technology, India

A Methodology for Improvement of Roba Multiplier for Electronic ApplicationsFull Text
Angila Rose Daniel and B. Deepa, Kerala technical university, India