Volume 2

December 2011, Volume 2, Number 4

A New Full Adder Cell for Molecular Electronics  
Mehdi Ghasemi, Mohammad Hossein Moaiyeri and Keivan Navi, Shahid Beheshti University G.C., Iran

A New Design Technique of Reversible BCD Adder Based on NMOS with Pass Transistor Gates  
Md. Sazzad Hossain1, Md. Rashedul Hasan Rakib1, Md. Motiur Rahman1, A. S. M. Delowar Hossain1 and Md. Minul Hasan2,
1Mawlana Bhashani Science & Technology University, Bangladesh and 2Amader Ltd, Bangladesh

FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS - II Based SOC  
Bolla Leela Naresh, N. V. Narayana Rao and Addanki Purna Ramesh, Sri Vasavi Engg College, India

Design of Reversible Sequential Circuit Using Reversible Logic Synthesis  
Md. Belayet Ali, Md. Mosharof Hossin and Md. Eneyat Ullah, Mawlana Bhashani Science and Technology University,

Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate  
Manoj Kumar1, Sandeep K. Arya1 and Sujata Pandey2,1Guru Jambheshwar University of Science & Technology, India and
2Amity University, India

Fault Modeling of Combinational and Sequential Circuits at Register Transfer Level  
M. S. Suma1 and K. S. Gurumurthy2, 1R. V. College of Engineering, India and 2U. V. College of Engineering, India

A Novel Approach to Minimize Spare Cell Leakage Power Consumption During Physical Design Implementation  
Vasantha Kumar B. V. P1 , N. S. Murthy Sharma2 , K. Lal Kishore3 and Jibanjeet Mishra1, 1 Synopsys (India) Pvt. Ltd, India,
2 SV Institute of Engineering and Technology, India and 3 JNT University, India

VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology  
Rita M. Shende and Pritesh R. Gumble, Sipna's College of Engineering & Technology, India

An Efficient FPGA Implemenation of MRI Image Filtering and Tumour Characterization Using XILINX System
S. Allin Christe, M. Vignesh and A. Kandaswamy, PSG College of Technology, India

Design and ASIC Implemenatation of DUC/DDC for Communication Systems  
Naagesh S. Bhat, Green Mil International Ltd., India

Low Power Low Voltage Bulk Driven Balanced OTA  
Neha Gupta, Sapna Singh, Meenakshi Suthar and Priyanka Soni, Mody Institute of Technology and Science, India

Using CMOS Sub-Micron Technology VLSI Implementation of Low Power, High Speed SRAM Cell and DRAM Cell  
Viplav A. Soliv and Ajay A. Gurjar, Sipna's college of Engineering & Technology, India

A Novel Methodology for Thermal Aware Silicon Area Estimation for 2D & 3D MPSoCs  
Ramya Menon C. and Vinod Pangracious, Rajagiri School of Engineering & Technology, India

Design of Low Write-Power Consumption SRAM Cell Based on CNTFET at 32nm Technology  
Rajendra Prasad S1, B K Madhavi2 and K Lal Kishore3, 1ACE Engineering College, India, 2GCET, India and 3JNT University,

Optimized Design of 2D Mesh NOC Router using Custom SRAM & Common Buffer Utilization  
Bhavana Pote1,V. N. Nitnaware1 and S. S. Limaye2, 1Ramdeobaba Kamla Nehru College of Engg, India and 2Jhulelal Institute of Technology, India

September 2011, Volume 2, Number 3

A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits  
Mouna Karmani1, Chiraz Khedhiri1, Belgacem Hamdi1 and Brahim Bensalem2,1Electronics and Microelectronics Laboratory,
Tunisia and 2Intel Corporation, USA

Test Generation for Analog and Mixed-Signal Circuits Using Hybrid System Models  
Tarik NAHHAL1 and Thao Dang2,1Hassan II University, Morocco and 2VERIMAG, France

A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic  
P. Prasad Rao and K. Lal Kishore, JNTU-Hyderabad, India

FPGA Implementation of Soft Output Viterbi Algorithm Using Memoryless Hybrid Register Exchange Method  
R .D. Kadam and S. L. Haridas, RTM Nagpur University, India

Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power Applications  
Subhra Dhar1, Manisha Pattanaik1, P. Rajaram2,1ABV-Indian Institute of Information Technology and Management, India and
2Jiwaji University, India

Power Comparison of CMOS and Adiabatic Full Adder Circuits  
Y. Sunil Gavaskar Reddy and V. V. G. S. Rajendra Prasad, JNT University, India

Sub Ten Micron Channel Devices Achieved by Vertical Organic Thin Film Transistor  
Abdul Rauf Khan1, S. S. K. Iyer2,1Graphic Era University, India and 2IIT-Kanpur, India

Pipelined Architecture of 2D-DCT, Quantization and ZigZag Process for JPEG Image Compression Using VHDL   
T. Pradeepthi and Addanki Purna Ramesh, Sri Vasavi Engg College, India

Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip   
Rehan Maroofi1,V. N. Nitnaware1 and S. S. Limaye2,1Ramdeobaba Kamla Nehru College of Engg, India and 2Jhulelal Institute of Technology, India

Performance analysis of DWT based OFDM over FFT based OFDM and implementing on FPGA   
Veena M. B and M. N. Shanmukha Swamy, SJCE, India

Design and Implementation of FPGA Based Signal Processing Card   
Priya Gupta1 and Deepak Gupta2,1Banasthali University, India and 2Alpine System, India

Design of a CMOS Bandgap Reference with Low Temperature Coefficient and High Power Supply Rejection Performance   
Abhisek Dey and Tarun Kanti Bhattacharyya, Indian Institute of Technology-Kharagpur, India

Area Optimized FPGA Implementation for Generation of Radar Pulse Compression Sequences   
P. Tirumala rao1, P. Siva kumar1, Y.V. Apparao2, Y. Madhu babu2,1Vignan institute of information technology, India and
2GITAM University, India

Special Issue on "VLSI - 2011"

Software and Hardware Design Challenges in Automotive Embedded System   
Rajeshwari Hegde1, Geetishree Mishra1, K S Gurumurthy2,1BMS College of Engineering, India and 2UVCE, India

Power Aware Physical Model for 3D ICs   
Yasmeen Hasan, Integral University, India

Linearity and Analog Performance Analysis of Double Gate Tunnel FET: Effect of Temperature and Gate Stack   
Rakhi Narang1, Manoj Saxena1, R. S. Gupta2and Mridula Gupta1,1University of Delhi, India and 2Maharaja Agrasen Institute
of Technology, India

Brauns Multiplier Implementation using FPGA with Bypassing Techniques   
Anitha R and Bagyaveereswaran V, VIT University, India

Modelling and Simulation of 128-Bit Crossbar Switch for Network On Chip   
Mohammad Ayoub Khan1 and Abdul Quaiyum Ansari2, 1Ministry of Communications and Information Techology, India and
2Jamia Millia Islamia, India

Impact of Interface Fixed Charges on the Performance of the Channel Material Engineered Cylindrical Nanowire
Rajni Gautam1, Manoj Saxena1, R. S. Gupta2 and Mridula Gupta1, 1University of Delhi, India and 2Maharaja Agrasen
Institute of Technology, India

Reducing power in using different technologies using FSM architecture   
Himani Mitta, Dinesh Chandra and Sampath Kumar, J. S. S. Academy of Technical Education, India

June 2011, Volume 2, Number 2

A BIST Generator CAD Tool for Numeric Integrated Circuits  
Chiraz Khedhiri1, Mouna Karmani1 and Belgacem Hamdi1,2, 1Electronic & Microelectronics'LAB, Tunisia and 2ISSAT, Tunisia

A Novel Approach for Lower Power Design in Turbo Coding System  
Dayadi.Lakshmaiah1, M. V. Subramanyam2 and K. Sathaya Prasad3, 1Sree Dattha Engineering and Science, India, 2Santhi Ram
Engineering College, India and 3JNTU, India

Design and test challenges in Nano-scale analog and mixed CMOS technology  
Mouna Karmani, Chiraz Khedhiri and Belgacem Hamdi, Electronics & Microelectronics Laboratory, Tunisia

Performance Comparison of RF CMOS Low Noise Amplifiers in 0.18-m technology scale  
M. Sumathi1 and S. Malarvizhi2, 1Sathyabama University, India and 2SRM University, India

Design of optimized Interval Arithmetic Multiplier  
Rajashekar B.Shettar and R. M. Banakar, BVB College of Engg and Technology, India

Performance of Different CMOS Logic Styles for Low Power and High Speed  
Sreenivasa Rao.Ijjada, Ayyanna. G, G. Sekhar Reddy and V. Malleswara Rao, GITAM University, India

New Design Methodologies for High-Speed Mixed-Mode CMOS Full Adder Circuits  
Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, M.N.N.I.T, India

A New Approach to Design Low Power CMOS Flash A/D Converter  
Sudakar S. Chauhan1, S. Manabala2, S. C. Bose2 and R. Chandel3, 1Graphic Era University, India, 2CEERI, India,
3National Institute of Technology - Hamirpur, India

A Bus Encoding to Reduce Crosstalk Noise Effect in System on Chip  
J. Venkateswara Rao1 and A. V. N. Tilak2, 1Vignan Institute of Technology & Science, India and 2Gudlavalleru Engineering
College, India

March 2011, Volume 2, Number 1

High Speed Multiple Valued Logic Full Adder Using Carbon Nano Field Effect Transistor  
Ashkan Khatir, Shaghayegh Abdolahzadegan and Iman Mahmoudi, Islamic Azad University, Iran

Performance Evaluation of FD-SOI MOSFETS for Different Metal Gate Work Function  
Deepesh Ranka, Ashwani K. Rana, Rakesh Kumar Yadav, Kamalesh Yadav and Devendra Giri,
National Institute of Technology - Hamirpur, India

Physical Scaling Limits of FinFET Structure: A Simulation Study  
Gaurav Saini and Ashwani K Rana, National Institute of Technology - Hamirpur, India

Design and Implementation of Area and Power Optimised Novel Scanflop  
R. Jayagowri1 and K. S. Gurumurthy2, 1Jawaharlal Nehru Technological University, India and 2Visveswaraya College
of Engineering, India

Optimization Techniques for Source Follower Based Track-and-Hold Circuit for High Speed Wireless Communication  
Manoj Kumar1 and Gagnesh Kumar2, 1Vidya College of Engineering, India and 2NIT - Hamirpur, India

Impact of Strain and Channel Thickness on Performance of Biaxial Strained Silicon MOSFETs  
Neha Sharan and Ashwani K. Rana, National Institute of Technology - Hamirpur, India

Design of a high frequency low voltage CMOS operational amplifier  
Priyanka Kakoty, Tezpur University, India

Design Approach for Fault Tolerance in FPGA Architecture  
Shweta S. Meshram1 and Ujwala A. Belorkar2, 1Government College of Engineering & Technology, Amravati, India and
2Hanuman Vyayam Prasarak Mandal's College of Engineering & Technology, India

Design and Analysis of Second and Third Order PLL at 450MHz  
B. K. Mishra, Sandhya Save and Swapna Patil, Mumbai University, India

Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology  
Ujwala A. Belorkar1 and S. A. Ladhake2, 1Hanuman Vyayam Prasarak Mandal's College of Engineering & Technology, India
and 2Sipana's College of Engineering & Technology, India