A New Efficient FPGA Design of Residue-to-Binary Converter
Edem Kwedzo Bankas and Kazeem Alagbe Gbolagade, University for Development Studies, Ghana
Accelerating System Verilog UVM Based VIP to Improve Methodology for Verification of Image Signal Processing Designs Using HW Emulator
Abhishek Jain1,2, Piyush Kumar Gupta1, Hima Gupta2 and Sachish Dhar1, 1STMicroelectronics, India and 2Jaypee Institute of Information Technology, India
Analysis of Pocket Double Gate Tunnel FET for Low Stand by Power Logic Circuits
Kamal K. Jha and Manisha Pattanaik, ABV- Indian Institute of Information Technology and Management, India
An Integrated-Approach for Designing and Testing Specific Processors
Cesar Giacomini Penteado1, Edward David Moreno2, S�rgio Takeo Kofuji1, 1University of Sao Paulo (USP), Brazil and 2Federal University of Sergipe, Brazil
Low Cost Reversible Signed Comparator
Farah Sharmin1, Rajib Kumar Mitra2, Rashida Hasan3, Anisur Rahman4, 1,3University of Dhaka, Bangladesh, 2Patuakhali Science and Technology University, Bangladesh and 4Daffodil International University, Bangladesh
Low Power Reduced Instruction Set Architecture Using Clock Gating Technique
M. Kamaraju and G. Chinavenkateswararao, Gudlavalleru Engineering College, India
Design and Implementation of Complex Floating Point Processor Using FPGA
Murali Krishna Pavuluri and T. S. R. Krishna Prasad and Ch. Rambabu, Gudlavalleru Engineering College, India
A New Improved MCML Logic for DPA Resistant Circuits
A. K. Tripathy, A. Prathiba and V. S. Kanchana Bhaaskaran, Vellore Institute of Technology, India
Static Power Optimization Using Dual Sub-Threshold Supply Voltages in Digital CMOS VLSI Circuits
K. Srilakshmi, Y. Syamala and A. Suvir Vikram, Gudlavalleru Engineering College, India
Design of Low Power CMOS Logic Circuits Using Gate Diffusion Input (GDI) Technique
Y. Syamala, K. Srilakshmi and N. Somasekhar Varma, Gudlavalleru Engineering College, India
Design of Ultra Low Power 8-Channel Analog Multiplexer Using Dynamic Threshold for Biosignals
D. Hari Priya1, P. Rama Krishna2, V. Rajesh1 and K. S. Rao3, 1KL University, India and 1,2,3Anurag Group of Institutions, India
A 10 dBm-25 dBm, 0.363 mm2 Two Stage 130 nm RF CMOS Power Amplifier
Shridhar R. Sahu and A. Y. Deshmukh, G. H. Raisoni College of Engineering, India
Extended K-Map for Minimizing Multiple Output Logic Circuits
Palash Das1 and Bikromadittya Mondal2, 1Bengal Engineering and Science University, India and 2B P Poddar Institute of Management and Technology, India
Analog Modeling of Recursive Estimator Design with Filter Design Model
R. Rajendra prasad1, M. V. Subramanyam2 and K. Satya Prasad3, 1N. B. K. R. Institute of Science and Technology, India, 2Santhi Ram Engineering College, India and 3JNTU, India
Performance Analysis of Modified QSERL Circuit
Shipra Upadhyay, R. A. Mishra and R. K. Nagaria, Motilal Nehru National Institute of Technology, India
Design of High Efficiency Two Stage Power Amplifier in 0.13�M RF CMOS Technology for 2.4GHZ WLAN Application
Shridhar R. Sahu and A.Y. Deshmukh, G. H. Raisoni College of Engineering, India
A New Low Voltage P-MOS Bulk Driven Current Mirror Circuit
Anuj Dugaya and Laxmi Kumre, Maulana Azad National Institute of Technology, India
Low Power-Area Designs of 1Bit Full Adder in Cadence Virtuoso Platform
Karthik Reddy. G, G. Pulla Reddy Engineering college, India
Design of Three Bit Analog-To-Digital Converter (ADC) Using Spatial Wavefunction Switched (SWS) FETS
Supriya Karmakar, Intel Corporation, USA
Hardware Efficient Scaling Free Vectoring and Rotational Cordic for DSP Applications
Anita Jain and Kavita Khare, MANIT, India
Low Power Dual Edge - Triggered Static D Flip-Flop
Anurag, Gurmohan Singh and V. Sulochana, Centre for Development of Advanced Computing, India
Crosstalk Minimization for Coupled RLC Interconnects Using Bidirectional Buffer and Shield Insertion
Damanpreet Kaur and V.Sulochana, Centre for Development of Advanced Computing, India
CMOS Low Power Cell Library for Digital Design
Kanika Kaur1 and Arti Noor2, 1JJTU, India and 2CDAC, India
Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit
Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A Kulkarni, H .R. Bhagyalakshmi and M. K. Venkatesha, Visvesvaraya Technological University, India
Design and Implementation of Car Parking System on FPGA
Ramneet Kaur and Balwinder Singh, Centre for Development of Advanced Computing, India
A Rail-To-Rail Hign Speed Class-AB CMOS Buffer with Low Power and Enhanced Slew Rate
Sadhana Sharma, Abhay Vidyarthi and Shyam Akashe, ITM University, India
Design of a Programmable Low Power Low Drop-Out Regulator
Jayanthi Vanama1 and G. L. Sampoorna2, 1Powerwave Technologies Pvt. Ltd., India and 2CONEXANT Systems Pvt. Ltd., India
Design and Performance Analysis of ZBT SRAM Controller
Smriti Sharma and Balwinder Singh, Centre for Development of Advanced Computing, India
Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS) Analog to Digital Converter
Arun Kumar Sunaniya and Kavita Khare, MANIT, India
Power Efficient Carry Propagate Adder
Laxmi Kumre, Ajay Somkuwar and Ganga Agnihotri, MANIT, India
Enhancing Multiplier Speed in Fast Fourier Transform Based on Vedic Mathematics
R. P. Meenaakshi Sundari, D. Subathra and M. S. Dhanalaxmi, Sasurie College of Engineering, India
An Investigation Into the Relationships Between Logical Operations
Maher A. Nabulsi and Ahmad Abusukhon, Al-Zaytoonah Private University, Jordon
Evaluation of Optically Illuminated Mosfet Characteristics by Tcad Simulation
Prerana Jain1 and Mishra B.K2, 1SKVM's NMIMS,Vile Parle(W), India and 2Thakur College of Engg and Technology, India
Establishing A Molecular Communication Channel for Nano Networks
Prachi Raut and Nisha Sarwade, VJTI,India
FGMOS Based Low-Voltage Low-Power High Output Impedance Regulated Cascode Current Mirror
Abhinav Anand, Sushanta K. Mandal, Anindita Dash and B. Shivalal Patro, KIIT University, India
Analysis of Small-Signal Parameters of 2-D Modfet with Polarization Effects for Microwave Applications
Ramnish Kumar1, Sandeep K Arya1 and Anil Ahlawat2, 1GJUST-Hisar, India and 2KIET-Ghajiabad, India
The Design of a Low Power Floating Gate Based Phase Frequency Detector and Charge Pump Implementation
Md Monirul Islam and Ankit Shivhare, KIIT University, India
Smart Multicrossbar Router Design in NOC
Bhavana Prakash Shrivastava and Kavita Khare, Maulana Azad National Institute of Technology, India
Design Low Power Encoder for Threshold Inverter Quantization Based Flash ADC Converter
Mamta Gurjar and Shyam Akashe, ITM University, India
An Efficient CNTFET Based 7-Input Minority Gate
Samira Shirinabadi Farahani, Ronak Zarhoun, Mohammad Hossein Moaiyeri and Keivan Navi, Shahid Beheshti University, Iran
Realization of Transmitter and Receiver Architecture for Downlink Channels in 3-GPP LTE
S. Syed Ameer Abbas1, J. Rahumath Nisha1, M. Beril Sahaya Mary1 and S. J. Thiruvengadam2, 1Mepco Schlenk Engineering College, India and 2Thiagarajar College of Engineering, India
Matrix Code Based Multiple Error Correction Technique for N-Bit Memory Data
Sunita M. S and Kanchana Bhaaskaran V. S, VIT University, India
A Novel Power Reduction Technique for Dual-Threshold Domino Logic in Sub-65nm Technology
Tarun Kr. Gupta and Kavita Khare, MANIT, India
Dual Field Dual Core Secure Cryptoprocessor on FPGA Platform
C. Veeraraghavan1 and K. Rajendran2, 1Sri Krishna Arts and Science College, India and 2Government Arts College for Women, India
Ternary Tree Asynchronous Interconnect Network for GALS' SOC
Vivek E. Khetade and S. S. Limaye, Rashtrasant Tukdoji Maharaj Nagpur university, India
A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric
Anil Yadav1, Justin Stander2, Alex K. Jones2 and Gayatri Mehta1, 1University of North Texas, USA and 2University of Pittsburgh, USA
Implementation of Compaction Algorithm for ATPG Generated Partially Specified Test Data
Vaishali Dhare and Usha Mehta, Nirma University, India
A Multi-Objective Perspective for Operator Scheduling Using Finegrained DVS Architectures
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta and Ajit Pal, Indian Institute of Technology- Kharagpur, India
Reduction of Bus Transition for Compressed Code Systems
S. R. Malathi and R. Ramya Asmi, Sri Venkateswara College of Engineering, India
