A New Transistor Sizing Approach for Digital Integrated Circuits Using Firefly Algorithm
Nima Talebpour Anaraki, Mehdi Dolatshahi and Mohammad Hossein Nadimi Shahraki, Islamic Azad University, Iran
Advanced Verification Methodology for Complex System on Chip Verification
G. Renuka1, V. Ushashree2 and P. Chandrasekhar Reddy3, 1SREC, India, 2JBIET, India and 3JNTU, India
Design of a Low-Power 1.65 GBPS Data Channel for HDMI Transmitter
Ajay Agrawal and R. S. Gamad, Shri Govindram Seksaria Institute of Technology and Science, India
Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clock Gating Technique
T. Subhashini and M. Kamaraju, Gudlavalleru Engineering College, India
A Novel Methodology of Simulation and Realization of Various OPAMP Topologies in 0.18μm CMOS Technology Using MATLAB
E. Srinivas1, N. Balaji2 and L. Padma sree3, 1JNTU-Hyderabad, India, 2JNTU-Vijayanagaram, India and 3VNR VJIET, India
FPGA Implementation of Moving Object and Face Detection Using Adaptive Threshold
Sateesh Kumar H.C1, Sayantam Sarkar2, Satish S Bhairannawar3, Raja K.B4 and Venugopal K.R4, 1SaiVidya Institute of Technology, India, 2VijayaVittala Institute of Technology, India, 3DayanandaSagar College of Engineering, India and 4University Visvesvaraya College of Engineering, India
Area, Delay and Power Analysis of Built in Self Repair Using 2-D Redundancy
Aman Kumar Sabnani and Balwinder Singh, Centre for Development of Advanced Computing, India
Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique
Simran kaur, Balwinder Singh and D. K Jain, Centre for Development of Advanced Computing, India
A Technique for Designing High Speed Noise Immune CMOS Domino High Fanin Circuits in 16nm Technology
P. Koti Lakshmi and Rameshwar Rao, Osmania University, India
Design of a Compact Reversible Read-Only-Memory with MOS Transistors
Sadia Nowrin, Papiya Nazneen and Lafifa Jamal, University of Dhaka, Bangladesh
Feasible Methodology for Optimization of a Novel Reversible Binary Compressor
Neeraj Kumar Misra, Mukesh Kumar Kushwaha, Subodh Wairya and Amit Kumar, Institute of Engineering and Technology, India
Design Approach for Fault Recoverable ALU with Improved Fault Tolerance
Ankit K V, S Murali Narasimham and Viajya Prakash A M, Bangalore Institute of Technology, India
A Novel Handover Algorithm for LTE Based Macro-Femto Heterogeneous Networks
Bhargavi D K and Vijaya Prakash A M, Bangalore Institute of Technology, India
Architecture of a Novel Configurable Communication Processor for SDR
Amiya Karmakar1, Amitabha Sinha2, Pratik Kumar Sinha3 and Pijush Biswas4, 1West Bengal University of Technology, India, 2B. C. Roy Engineering College, India, 3N. I. T - Durgapur, India and 4N.S.H.M, India
ASIC Implementation of I2C Master Bus Controller Firm IP Core
S Sindhu, Vijaya Prakash A M and Ankit K V, Bangalore Institute of Technology, India
A Novel Architecture of RNS Based Lifting Integer Wavelet Transform (IWT) and Comparative Study with Other Binary and Non-Binary DWT
Souvik Saha1, Uttam Narendra Thakur1 and Prof Amitabha Sinha2, 1University of Engineering and Management, India and 2Dr. BC Roy Engineering College, India
Mitigation of Soft Errors on 65NM Combinational Logic Gates via Buffer Gate
Ali Hosseini1 and Hadi Jahanirad2, 1Islamic Azad University, Iran and 2Kurdistan University, Iran
Design and Implementation of 10 Bit, 2MS/s Split SAR ADC Using 0.18um CMOS Technology
Kalmeshwar N. Hosur1, Girish V. Attimarad2 and Harish M. Kittur3, 1S.D.M. College of Engineering & Technology, India, 2Dayanand Sagar College of Engineering, India and 3VIT University, India
Evaluation of ATM Functioning Using VHDL and FPGA
Manali Dhar, Debolina Roy and Tamosha Saha, DSCSDEC, India
Schottky Tunneling Source Impact Ionization Mosfet (STS-IMOS) with Enhanced Device Performance
Sangeeta Singh and P. N. Kondekar, Indian Institute of Information Technology, India
SAF Analyses of Analog and Mixed Signal VLSI Circuit : Digital to Analog Converter
Vaishali Dhare and Usha Mehta, Nirma University, India
Minimally Buffered Router Using Weighted Deflection Routing for Mesh Network on Chip
Simi Zerine Sleeba and Mini M.G, Cochin University of Science and Technology, India
Tracking Cancer Patients Medical History Using Wireless Emerging Technology : Near Field Communication
Shivang Bhagat, Darshana Upadhyay and Parita Oza, Nirma Institute of Technology, India
Dynamic Floating Output Stage for Low Power Buffer Amplifier for LCD Application
Hari Shanker Srivastava and R.K Baghel, MANIT - Bhopal, India
A Low Power CMOS Analog Circuit Design for Acquiring Multichannel EEG Signals
G.Deepika1 and Dr. K.S.Rao2, 1RRS College of Engineering & Technology, India and 2ANURAG Group of Institutions, India
