Simultaneous Optimization of Standby and Active Energy for Sub-Threshold Circuits
Ali T. Shaheen and Saleem M. R. Taha, University of Baghdad, Iraq
VLSI Implementation of Area Efficient 2-Parallel FIR Digital Filter
L Kholee Phimu and Manoj Kumar, NIT Manipur, India
500nW A Low Power Switched Capacitor Based Active Low Pass Filter for Biomedical Applications
U. Gnaneshwara Chary, L.Babitha and Vandana.Ch, BVRIT - Telangana, India
Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N
Monica Mankar1, Gajendra Asutkar2 and Pravin Dakhole1, 1Yeshwantrao Chavan college of Engineering, India and 2Priyadarshani Institute of Engineering and Technology, India
Single-Port Five-Transistor SRAM Cell with Reduced Leakage Current in Standby
Chien-Cheng Yu and Ming-Chuen Shiau, Hsiuping University of Science and Technology, Taiwan
Design of Digital PLL Using Optimized Phase Noise VCO
Purnima1, Radha B.L1 and Kumaraswamy K.V2, 1Bangalore Institute of Technology, India and 2Trident Techlabs Private limited, India
Implementation of SDC-SDF Architecture for Radix-4 FFT
G. Deeshma Venkatakanakadurga and G. R. L. V. N. Srinivasaraju, Shri Vishnu Engineering College for Women, India
Leakage Reduction Technique and Analysis of CMOS D Flip Flop
Sridhara K and G S Biradar, P D A College of Engineering, India
Glitch Analysis and Reduction in Digital Circuits
Ronak Shah, Dharmsinh Desai University, India
Low Power-Area Design of Full Adder Using Self Resetting Logic with GDI Technique
Simran Khokha1 and K.Rahul Reddy2, 1University of Delhi, India and 2Sharda University, India
Dualistic Threshold Based Min-Max Method for Voice Signal Enhancement
Pushpraj Tanwar and Ajay Somkuwar, Maulana Azad National Institute of Technology, India
Folded Architecture for Non Canonical Least Mean Square Adaptive Digital Filter Used in Echo Cancellation
Pradnya Zode and A.Y.Deshmukh, G.H.Raisoni College of Engineering, India
Designing an Efficient Approach for JK and T Flip-Flop with Power Dissipation Analysis Using QCA
Shraddha Pandey, Sonali Singh and Subodh Wairya, Institute of Engineering and Technology - Lucknow, India
Optimal Unate Decomposition Method for Synthesis of Mixed CMOS VLSI Circuits
Sai Praveen Kadiyala and Debasis Samanta, Indian Institute of Technology - Kharagpur, India
Comparative Design of Regular Structured Modified Booth Multiplier
Ram RackshaTripathi and S. G. Prakash, University of Allahabad, India
Modified Micropipline Architecture for Synthesizable Asynchronous FIR Filter Design
Basel Halak and Hsien-Chih Chiu, Southampton University, United Kingdom
Low Power, Low Noise Amplifiers Design and Analysis for RF Receiver Front end Using 90NM CMOS Technology Used for WIMAX Applications
M. Ramana Reddy1, N. S Murthy Sharma2 and P. Chandra Sekhar1, 1Osmania University, India, 2SIT, India
Design and Implementation of an Improved Carry Increment Adder
Aribam Balarampyari Devi1, Manoj Kumar1 and Romesh Laishram2, 1National Institute of Technology, India and 2Manipur Institute of Technology, India
