Most Cited Articles

Most Cited Articles – 2017

A Prediction Method of Gesture Trajectory Based on Least Squares Fitting Model
M Cai, VLSICS Journal, Vol.8, No.1, February 2017, PP. 1-18
DOI : 10.5121/vlsic.2017.8101

Design of Low Power Medical Device
C Wei, VLSICS Journal ,Vol.8, No.2, April 2017, PP. 1-7
DOI : 10.5121/vlsic.2017.8201

Zigbee Transmitter for IoT Wireless Devices
A Mounica, VLSICS Journal, Vol.8, No.5, October 2017, PP. 1-13
DOI : 10.5121/vlsic.2017.8501

Most Cited Articles – 2016

Designing an Efficient Approach for JK and T Flip-Flop with Power Dissipation Analysis Using QCA
P Shraddha, VLSICS Journal, Vol.7, No.3, June 2016, PP. 1-20
DOI : 10.5121/vlsic.2016.7303

Design and Implementation of an Improved Carry Increment Adder
D Aribam Balarampyari, VLSICS Journal, Vol.7, No.1, February 2016, PP. 1-7
DOI : 10.5121/vlsic.2016.7103

Most Cited Articles – 2015

Design and Performance Analysis of Various Adders and Multipliers Using GDI Technique
DKJ Simran kaur, VLSICS Journal, Vol.6, No.5 , October 2015, PP. 1-12
DOI : 10.5121/vlsic.2015.6504

FPGA Implementation of Moving Object and Face Detection Using Adaptive Threshold
PRR P. Koti Lakshmi, VLSICS Journal, Vol.6, No.5, October 2015, PP. 1-11
DOI : 10.5121/vlsic.2015.6505

A Technique for Designing High Speed Noise Immune CMOS Domino High Fanin Circuits in 16nm Technology
P. Koti Lakshmi, VLSICS Journal, Vol.6, No.5, October 2015, PP. 1-11
DOI : 10.5121/vlsic.2015.6505

Design of a Compact Reversible Read-Only-Memory with MOS Transistors
LJ Sadia Nowrin, VLSICS Journal, Vol.6, No.5, October 2015, PP. 1-16
DOI : 10.5121/vlsic.2015.6506

Most Cited Articles – 2014

Implementation of an Arithmetic Logic Using Area Efficient Carry Lookahead Adder
SA Navneet Dubey, VLSICS Journal, Vol.5, No.6, December 2014, PP. 1-6
DOI : 10.5121/vlsic.2014.5604

Transistor Level Implementation of Digital Reversible Circuits
YS K.Prudhvi Raj, VLSICS Journal, Vol.5, No.6, December 2014, PP. 1-19
DOI : 10.5121/vlsic.2014.5606

An Operational Amplifier With Recycling Folded Cascode Topology And Adaptive Biaisng
AM Saumya Vij, VLSICS Journal, Vol.6, No.5, August 2014, PP. 1-14
DOI : 10.5121/vlsic.2014.5403

Design Of A Novel Current Balanced Voltage Controlled Delay Element
VBC Pooja Saxena, VLSICS Journal, Vol.5, No.5, June 2014, PP. 1-9
DOI : 10.5121/vlsic.2014.5304

Most Cited Articles – 2013

A New Efficient Fpga Design Of Residue-To-Binary Converter
KAG Edem Kwedzo Bankas ,VLSICS Journal ,Vol.4 ,No.6 ,December 2013, PP. 1-11
DOI : 10.5121/vlsic.2013.4601

Design Of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit
MKV Rakshith Saligram, VLSICS Journal, Vol.4, No.3, June 2013, PP. 1-16
DOI : 10.5121/vlsic.2013.4306

Design And Implementation Of Car Parking System On Fpga
BS Ramneet Kaur , VLSICS Journal ,Vol.4 ,No.3 ,June 2013, PP. 1-9
DOI : 10.5121/vlsic.2013.4307

W Low Power-Area Designs Of 1bit Full Adder In Cadence Virtuoso Platform
K Reddy, VLSICS Journal, Vol.4, No.4, August 2013, PP. 1-10
DOI : 10.5121/vlsic.2013.4406

Most Cited Articles - 2012

Leakage Power Reduction And Analysis Of Cmos Sequential Circuits
M. Janaki Rani and S. Malarkann, VLSICS Journal, Vol.3, No.1, February 2012, PP. 13-23
DOI : 10.5121/vlsic.2012.3102

Area, Delay and Power Comparison of Adder Topologies
R.UMA,Vidya Vijayan , M. Mohanapriya and Sharon Paul, VLSICS Journal, Vol.3, No.1, February 2012, PP. 153-168
DOI : 10.5121/vlsic.2012.3113

Wishbone bus Architecture-A Survey and Comparison Mohandeep
Sharma and Dilip Kumar, VLSICS Journal, Vol.3, No.2, April 2012, PP. 107-124
DOI : 10.5121/vlsic.2012.3210

Comparative Performance Analysis Of XOR-XNOR Function Based High Speed CMOS Full Adder Circuits For Low Voltage VLSI Design
Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, VLSICS Journal, Vol.3, No.2, April 2012, PP. 221-242
DOI : 10.5121/vlsic.2012.3219

Finite State Machine based Vending Machine Controller with Auto-Billing Features
Ana Monga, and Balwinder Singh, VLSICS Journal, Vol.3, No.2, April 2012, PP. 19-28
DOI : 10.5121/vlsic.2012.3202

Low Power Dynamic Buffer Circuits
Amit Kumar Pandey1, Ram Awadh Mishra and Rajendra Kumar Nagaria, VLSICS Journal, Vol.3, No.5, October 2012, PP. 53-65
DOI : 10.5121/vlsic.2012.3505

Design of Reversible Multipliers for linear filtering Applications in DSP
Rakshith Saligram and Rakshith T.R, VLSICS Journal, Vol.3, No.6, December 2012, PP. 67-77
DOI : 10.5121/vlsic.2012.3606

Most Cited Articles - 2011

Design And Analysis of Second And Third Order PLL At 450 Mhz
B. K. Mishra, Sandhya Save and Swapna Patil, VLSICS Journal, Vol.2, No.1, March 2011, PP. 97-114
DOI : 10.5121/vlsic.2011.2109

Design of A High Frequency Low Voltage CMOS Operational Amplifier
Priyanka Kakoty, VLSICS Journal, Vol.2, No.1, March 2011, PP. 73-85
DOI : 10.5121/vlsic.2011.2107

High Speed Multiple Valued Logic Full Adder Using Carbon Nano Tube Field Effect Transistor
Ashkan Khatir , Shaghayegh Abdolahzadegan and Iman Mahmoudi, VLSICS Journal, Vol.2, No.1, March 2011, PP. 1-9
DOI : 10.5121/vlsic.2011.2101

Design And Test Challenges In Nano-Scale Analog And Mixed CMOS Technology
Mouna Karmani, Chiraz Khedhiri and Belgacem Hamdi, VLSICS Journal, Vol.2, No.2, June 2011, PP. 33-43
DOI : 10.5121/vlsic.2011.2203

A New Approach To Design Low Power Cmos Flash A/D Converter
Sudakar S. Chauhan, S. Manabala , S.C. Bose and R. Chandel, VLSICS Journal, Vol.2, No.2, June 2011, PP. 100-108
DOI : 10.5121/vlsic.2011.2208

Single Bit Full Adder Design Using 8 Transistors With Novel 3 Transistors XNOR Gate
Manoj Kumar, Sandeep K. Arya and Sujata Pandey, VLSICS Journal, Vol.2, No.4, December 2011, PP. 47-59
DOI : 10.5121/vlsic.2011.2405

Design of Reversible Sequential Circuit Using Reversible Logic Synthesis
Md. Belayet Ali , Md. Mosharof Hossin and Md. Eneyat Ullah, VLSICS Journal, Vol.2, No.4, December 2011, PP. 37-45
DOI : 10.5121/vlsic.2011.2404

Most Cited Articles - 2010

Arithmetic Operations In Multi-Valued Logic
Vasundara Patel, K S Gurumurthy, VLSICS Journal, Vol.1,No.1,March 2010, PP. 21-32
DOI : 10.5121/vlsic.2010.1101

Design of Low Power Phase Locked Loop (Pll) Using 45nm Vlsi Technology
Ms. Ujwala A. Belorkar and S.A.Ladhake, VLSICS Journal, Vol.1, No.2, June 2010, PP. 1-11
DOI : 10.5121/vlsic.2010.1201